/*
 * Copyright (c) 2024, Advanced Micro Devices, Inc.
 * All rights reserved.
 *
 * Author: Chris Lavin, Advanced Micro Devices, Inc.
 *
 * This file is part of RapidWright.
 *
 * Licensed under the Apache License, Version 2.0 (the "License");
 * you may not use this file except in compliance with the License.
 * You may obtain a copy of the License at
 *
 *     http://www.apache.org/licenses/LICENSE-2.0
 *
 * Unless required by applicable law or agreed to in writing, software
 * distributed under the License is distributed on an "AS IS" BASIS,
 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 * See the License for the specific language governing permissions and
 * limitations under the License.
 *
 */

/**
 *
 */
package com.xilinx.rapidwright.device;


/**
 * Generated on: Thu Nov 21 13:34:08 MST 2024
 * by: com.xilinx.rapidwright.release.SiteAndTileTypeUpdater
 *
 * Enumeration of IOStandard type for all valid devices within Vivado.
 */
public enum IOStandard {
    AIO12_LVAUX,
    ANALOG,
    ANALOG_SE,
    BLVDS_25,
    DEFAULT,
    DIFF_AIO12_LVAUX,
    DIFF_HSTL_I,
    DIFF_HSTL_II,
    DIFF_HSTL_II_18,
    DIFF_HSTL_II_DCI,
    DIFF_HSTL_II_DCI_18,
    DIFF_HSTL_II_T_DCI,
    DIFF_HSTL_II_T_DCI_18,
    DIFF_HSTL_I_12,
    DIFF_HSTL_I_18,
    DIFF_HSTL_I_DCI,
    DIFF_HSTL_I_DCI_12,
    DIFF_HSTL_I_DCI_18,
    DIFF_HSUL_12,
    DIFF_HSUL_12_DCI,
    DIFF_LVSTL05_10,
    DIFF_LVSTL05_10_HS,
    DIFF_LVSTL06_12,
    DIFF_LVSTL_11,
    DIFF_MOBILE_DDR,
    DIFF_POD10,
    DIFF_POD10_DCI,
    DIFF_POD11,
    DIFF_POD12,
    DIFF_POD12_DCI,
    DIFF_SSTL10,
    DIFF_SSTL11,
    DIFF_SSTL12,
    DIFF_SSTL12_DCI,
    DIFF_SSTL12_LVAUX,
    DIFF_SSTL12_T_DCI,
    DIFF_SSTL135,
    DIFF_SSTL135_DCI,
    DIFF_SSTL135_II,
    DIFF_SSTL135_R,
    DIFF_SSTL135_T_DCI,
    DIFF_SSTL15,
    DIFF_SSTL15_DCI,
    DIFF_SSTL15_II,
    DIFF_SSTL15_R,
    DIFF_SSTL15_T_DCI,
    DIFF_SSTL18_I,
    DIFF_SSTL18_II,
    DIFF_SSTL18_II_DCI,
    DIFF_SSTL18_II_T_DCI,
    DIFF_SSTL18_I_DCI,
    DIFF_UNDEFINED,
    HSLVDCI_15,
    HSLVDCI_18,
    HSTL_I,
    HSTL_II,
    HSTL_II_18,
    HSTL_II_DCI,
    HSTL_II_DCI_18,
    HSTL_II_T_DCI,
    HSTL_II_T_DCI_18,
    HSTL_I_12,
    HSTL_I_18,
    HSTL_I_DCI,
    HSTL_I_DCI_12,
    HSTL_I_DCI_18,
    HSUL_12,
    HSUL_12_DCI,
    LVCMOS10,
    LVCMOS11,
    LVCMOS12,
    LVCMOS12_LVAUX,
    LVCMOS15,
    LVCMOS18,
    LVCMOS25,
    LVCMOS33,
    LVDCI_15,
    LVDCI_18,
    LVDCI_DV2_15,
    LVDCI_DV2_18,
    LVDS,
    LVDS12,
    LVDS12_LVAUX,
    LVDS15,
    LVDS_25,
    LVPECL,
    LVSTL05_10,
    LVSTL05_10_HS,
    LVSTL06_12,
    LVSTL_11,
    LVTTL,
    MINI_LVDS_25,
    MIPI_CPHY,
    MIPI_DPHY,
    MIPI_DPHY_DCI,
    MIPI_DPHY_LVAUX,
    MOBILE_DDR,
    PCI33_3,
    POD10,
    POD10_DCI,
    POD11,
    POD12,
    POD12_DCI,
    PPDS_25,
    RSDS_25,
    SLVS_400_18,
    SLVS_400_25,
    SSTL10,
    SSTL11,
    SSTL12,
    SSTL12_DCI,
    SSTL12_LVAUX,
    SSTL12_T_DCI,
    SSTL135,
    SSTL135_DCI,
    SSTL135_II,
    SSTL135_R,
    SSTL135_T_DCI,
    SSTL15,
    SSTL15_DCI,
    SSTL15_II,
    SSTL15_R,
    SSTL15_T_DCI,
    SSTL18_I,
    SSTL18_II,
    SSTL18_II_DCI,
    SSTL18_II_T_DCI,
    SSTL18_I_DCI,
    SUB_LVDS,
    TMDS_33,
    UNDEFINED,
}
